Senior Design Lead

Job description

Open position 4 Exp :-- No particular number of years experience required once they meet the JD below , which implies a certain level of experience. Equally a person with 20 years experience doing power management is not useful as they cannot meet the mandatory parts of the JD. Job description for the analog circuit verification role below ------------------------------------------------------------------------------------------------------------------------------------------------- Mandatory • Good communicator in English in written and verbal form • Has some exposure, circuit design or analog verification, to serDes or clocking circuits at low or high data rates (minimum 1G) o Serdes circuits  Tx Output Driver, Tx serializer, Marching network, Termination circuits Rx CTLE, Rx DFE, RX deseilaizer Rx TISAR ADC, Piplelined ADC, Track and hold circuits passive and active, o Clocking circuits  PLL, DLL, ILO, Phase Interpolator, VCO (LC or Ring ), Charge Pump, PFD, TDC, PLL filter (integrating or proportional), prescalar, divider, clock buffering (CML or CMOS) • Highly skilled in Cadence Virtuoso toolset and use of Spectre-X (Cadence), AFS (Siemens) and Solido PVTMC/HSV (Siemens) simulation tools • Is strong at testbench creation given a circuit block spec • Uses automated measurements using MDL and/or Ocean to check simulations and for reporting • Good presentation skills in terms of generating and presenting simulation reports Desirable • Higher rates >10G on the above circuits • Circuit porting skills o Design tweaks and analog verification Key Responsibilities Open position 4 Exp :-- No particular number of years experience required once they meet the JD below , which implies a certain level of experience. Equally a person with 20 years experience doing power management is not useful as they cannot meet the mandatory parts of the JD. Job description for the analog circuit verification role below ------------------------------------------------------------------------------------------------------------------------------------------------- Mandatory • Good communicator in English in written and verbal form • Has some exposure, circuit design or analog verification, to serDes or clocking circuits at low or high data rates (minimum 1G) o Serdes circuits  Tx Output Driver, Tx serializer, Marching network, Termination circuits Rx CTLE, Rx DFE, RX deseilaizer Rx TISAR ADC, Piplelined ADC, Track and hold circuits passive and active, o Clocking circuits  PLL, DLL, ILO, Phase Interpolator, VCO (LC or Ring ), Charge Pump, PFD, TDC, PLL filter (integrating or proportional), prescalar, divider, clock buffering (CML or CMOS) • Highly skilled in Cadence Virtuoso toolset and use of Spectre-X (Cadence), AFS (Siemens) and Solido PVTMC/HSV (Siemens) simulation tools • Is strong at testbench creation given a circuit block spec • Uses automated measurements using MDL and/or Ocean to check simulations and for reporting • Good presentation skills in terms of generating and presenting simulation reports Desirable • Higher rates >10G on the above circuits • Circuit porting skills o Design tweaks and analog verification Skill Requirements Other Requirements Apply now Information at a Glance Why HCLTech? At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first. HCLTech is a global technology company, home to more than 230,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending September 2026 totaled $14.8 billion. • Disclaimer • Privacy Statement • Terms of use • Sitemap • Raise a Grievance • We use cookies on our site. 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