SOC Engineering Manager (IP Subsystems) Bengaluru, India Category: Engineering Posted: 11/10/2026 Job ID: 19527

Job description

Job Description Date posted 11/10/2026 Category Engineering Hire Type Employee Job ID 19527 Remote Eligible No Date Posted 11/10/2026 We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years building and leading teams that deliver subsystems and SoCs that actually ship, not just pass reviews. The difference between a subsystem that integrates cleanly and one that causes months of debug downstream is something you see coming from the architecture phase, and you know how to steer your team away from those cliffs before anyone writes RTL. You are technical enough to review a timing constraint file or debug a CDC violation yourself, but you also know when to step back and let your engineers solve it. Managing remote teams does not intimidate you because you have learned that clarity, trust, and rhythm matter more than proximity. You can sit in a customer call, extract what they actually need from what they say they want, and walk out with a plan your team can execute against. You think in workflows, not just deliverables. Automation, reusable frameworks, and AI-enabled tooling are not buzzwords to you, they are levers you pull to make your team faster and your subsystems more predictable. You push back when a requirement is vague or a timeline does not match reality, and you do it in a way that keeps the relationship intact. What You'll Be Doing • Lead the architecture, RTL design, integration, and front-end sign-off of DesignWare IP Subsystems from requirements through release • Manage a local engineering team in Bengaluru, driving execution across design, verification, and implementation while coordinating with global stakeholders • Own customer communication and requirements translation, ensuring deliverables align with what customers actually need and ship on time • Drive front-end implementation flows including synthesis timing closure using Fusion Compiler, SpyGlass CDC/RDC checks, low-power architecture, and Formality equivalence checking • Work hands-on when needed, reviewing RTL, debugging integration issues, authoring verification plans, or resolving critical bottlenecks in the subsystem lifecycle • Champion AI-enabled methods, workflow automation, and reusable engineering practices to improve team productivity, quality, and cycle time across subsystem programs • Collaborate across implementation, verification, DFT, and hardening teams to ensure clean handoffs and tape-out readiness The Impact You Will Have • Your subsystems will integrate into SoCs powering AI, automotive, 5G, and IoT products used by millions of people globally • You will shape how Synopsys subsystems are architected and delivered, setting the standard for quality, predictability, and execution velocity • Your team will deliver subsystems that reduce customer integration risk and accelerate their time to market • You will build a culture of automation and reuse that makes every subsequent program faster and more reliable • Your technical judgment will prevent costly late-stage design issues and keep programs on track through tape-out • You will mentor engineers who will go on to lead subsystem and SoC programs themselves • Your leadership will directly influence the adoption of AI-enabled workflows and modern engineering practices across the IP organization What You'll Need • Bachelor's or Master's degree in Electronics Engineering or related field with 10+ years of overall experience • 4 to 5 years managing engineering teams, ideally remote or distributed teams, with a track record of on-time delivery • Strong hands-on ASIC or SoC front-end design experience including RTL design, IP/subsystem integration, and taking designs from architecture through front-end execution • Deep expertise in at least one or two interface protocols such as AMBA (APB, AXI, CHI), DDR, PCIe, Ethernet, USB, UFS, or UCIe • Experience with front-end implementation flows including CDC/RDC checks using tools like SpyGlass or VC SpyGlass, UPF and low-power intent, design/timing constraints, and DFT handoff • Proficiency in SystemVerilog, TCL, Perl, or Python for RTL coding, scripting, and automation • Exposure to ASIC tape-out process, ideally at least one or two tape-outs, and understanding of how subsystems move through verification sign-off, DFT insertion, and hardening • Exposure to AI-enabled tools and automation frameworks applied to design, verification, or execution efficiency is a plus <h3 style='--tw-border-spacing-x: 0; --tw-border-spacing-y: 0; --tw-translate-x: 0; --tw-translate-y: 0; --tw-rotate: 0; --tw-skew-x: 0; --tw-skew-y: 0; --tw-scale-x: 1; --tw-scale-y: 1; --tw-pan-x: ; --tw-pan-y: ; --tw-pinch-zoom: ; --tw-scroll-snap-strictness: proximity; --tw-gradient-from-position: ; --tw-gradient-via-position: ; --tw-gradient-to-position: ; --tw-ordinal: ; --tw-slashed-zero: ; --tw-numeric-figure: ; --tw-numeric-spacing: ; --tw-numeric-fraction: ; --tw-ring-inset: ; --tw-ring-offset-width: 0px; --tw-ring-offset-color: #fff; --tw-ring-color: rgb(59 130 246/0.5); --tw-ring-offset-shadow: 0 0 #0000; --tw-ring-shadow: 0 0 #0000; --tw-shadow: 0 0 #0000; --tw-shadow-colored: 0 0 #0000; --tw-blur: ; --tw-brightness: ; --tw-contrast: ; --tw-grayscale: ; --tw-hue-rotate: ; --tw-invert: ; --tw-saturate: ; --tw-sepia: ; --tw-drop-shadow: ; --tw-backdrop-blur: ; --tw-backdrop-brightness: ; --tw-backdrop-contrast: ; --tw-backdrop-grayscale: ; --tw-backdrop-hue-rotate: ; --tw-backdrop-invert: ; --tw-backdrop-opacity: ; --tw-backdrop-saturate: ; --tw-backdrop-sepia: ; --tw-contain-size: ; --tw-contain-layout: ; --tw-contain-paint: ; --tw-contain-style: ; box-sizing: border-box; border: 0px solid rgb(229, 231, 235); font-size: 1.25rem; font-weight: 600; margin: 0px; padding-bottom: 0.25rem; padding-top: 0.375rem; line-height: 1.75rem; color: rgb(16, 27, 35); font-family: Roboto, "Roboto Fallback"; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; white-space: n