Digital Verification Senior Engineer Noida, India Category: Engineering Posted: 11/12/2026 Job ID: 19577

Job description

Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Job Description Date posted 11/12/2026 Category Engineering Hire Type Employee Job ID 19577 Date Posted 11/12/2026 We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent the last few years building verification environments that actually catch bugs before tapeout, and you know the difference between a testbench that looks complete and one that actually stresses the design. UVM is not just a framework you have heard about, it is something you have used to build real testbenches, debug real failures, and close coverage gaps that mattered. You are comfortable reading a specification, asking the questions that are not written down, and turning that into a verification plan that makes sense. When a simulation fails at 3pm, you do not wait for someone to tell you what to do. You dig into waveforms, trace the issue, and figure out whether it is a test problem, an environment problem, or an actual design bug. Protocols are not intimidating to you. Maybe you have worked with one already, maybe you have not, but you know how to read a spec, understand timing diagrams, and build checkers that enforce the rules. You are the kind of engineer who wants to get better, who asks good questions, and who does not need to be the smartest person in the room to contribute something real. At Synopsys, you will work with people who have been doing this for years and who will help you grow. What You'll Be Doing • Analyze design specifications and identify what needs to be verified, including functionality, interfaces, edge cases, and protocol compliance • Build and extend UVM-based verification environments in System Verilog, working alongside a technical lead to define architecture and reusable components • Write directed and constrained-random tests, implement functional checkers, and develop coverage models to track verification progress • Debug simulation failures by analyzing waveforms, logs, and coverage reports to isolate root causes in the testbench or design • Collaborate with design engineers to understand RTL changes and with the VIP team to integrate and leverage verification IP effectively • Contribute to test planning, code reviews, and process improvements that help the team close verification faster and with higher quality • Follow established verification methodologies and quality standards while identifying opportunities to improve flow efficiency The Impact You Will Have • Your verification environments will catch critical design issues before they reach silicon, saving months of debug time and reducing tapeout risk • The test scenarios and checkers you build will directly improve functional coverage closure and give the team confidence in design correctness • Your collaboration with design engineers will surface ambiguities and corner cases early, leading to cleaner RTL and fewer late-stage surprises • The verification IP and reusable components you help develop will be leveraged across multiple projects, accelerating future verification efforts • Your contributions to test planning and coverage analysis will help the team make data-driven decisions about when a block is ready to integrate • The questions you ask and the gaps you identify will strengthen specifications and improve the overall quality of the product • Your willingness to learn new protocols and methodologies will expand the team's capability and enable support for more complex designs What You'll Need • Bachelor's degree in Electronics Engineering, Electrical Engineering, or a closely related field • At least 3 years of hands-on experience in digital design verification • Proficiency in Verilog and System Verilog, with a working understanding of UVM methodology and testbench architecture • Experience writing and debugging testbenches, including constrained-random testing, functional coverage, and assertion-based verification <li style="--tw-border-spacing-x: 0; --tw-border-spacing-y: 0; --tw-translate-x: 0; --tw-translate-y: 0; --tw-rotate: 0; --tw-skew-x: 0; --tw-skew-y: 0; --tw-scale-x: 1; --tw-scale-y: 1; --tw-pan-x: ; --tw-pan-y: ; --tw-pinch-zoom: ; --tw-scroll-snap-strictness: proximity; --tw-gradient-from-position: ; --tw-gradient-via-position: ; --tw-gradient-to-position: ; --tw-ordinal: ; --tw-slashed-zero: ; --tw-numeric-figure: ; --tw-numeric-spacing: ; --tw-numeric-fraction: ; --tw-ring-inset: ; --tw-ring-offset-width: 0px; --tw-ring-offset-color: #fff; --tw-ring-color: rgb(59 130 246/0.5); --tw-ring-offset-shadow: 0 0 #0000; --tw-ring-shadow: 0 0 #0000; --tw-shadow: 0 0 #0000; --tw-shadow-colored: 0 0 #0000; --tw-blur: ; --tw-brightness: ; --tw-contrast: ; --tw-grayscale: ; --tw-hue-rotate: ; --tw-invert: ; --tw-saturate: ; --tw-sepia: ; --tw-drop-shadow: ; --tw-backdrop-blur: ; --tw-backdrop-brightness: ; --tw-backdrop-contrast: ; --tw-backdrop-grayscale: ; --tw-backdrop-hue-rotate: ; --tw-backdrop-invert: ; --tw-backdrop-opacity: ; --tw-backdrop-saturate: ; --tw-backdrop-sepia: ; --tw-contain-size: ; --tw-contain-layout: ; --tw-contain-paint: ; --tw-co