Physical IC Design Engineer

Job description

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom is searching for a Physical Verification PD Engineer to join the Asic Products Division. This position involves working with the advanced nodes to continue driving next generation Artificial Intelligence and Machine Learning ecosystems through our PCIe Switch Products, while leading world class performance, through our Enterprise Products. More specifically, this position will require in-depth knowledge of Foundary rules, DFM and experience in silicon tape-out and respins. Responsibilities: Execution of Chip level Physical Verification & Issue Resolution Work on setting up runsets for advance nodes and tool flows Manage and guide rules related to top level floorplan, I/O and bump planning Resolve physical design issues related to chip integration and assembly Provide technical direction on verification methodologies including DRC, LVS, ERC, and PERC Develop best practice guidelines for physical verification flows and runtime optimizations Preferred qualifications: Bachelors's degree in Electrical Engineering and 8+ years of experience in physical design and verification Master's degree in Electrical Engineering and 6+ years of experience in physical design and verification Hands-on experience in running physical verification (LVS,DRC,ERC,PERC) Experience in parasitic extraction tools i.e. StarRC, Quantus Experience with EDA tools and flows such as ICV, Calibre and Pegasus EDA tools Rule deck coding experience in ICV, Calibre or Pegasus EDA tools Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes and tape out experience Electrical Rule Checking (ERC/PERC): Analyze ESD (Electrostatic Discharge), latch-up, floating gates, and power-domain isolation vulnerabilities Density & Fill: Manage automated dummy metal, poly, and diffusion filling strategies to meet local and global density rules Yield Enhancement (DFM): Implement Design for Manufacturability fixes, including critical area analysis (CAA), via-doubling, and edge-displacement rules. Collaborate with physical design team to resolve critical top-level integration violations Experience in scripting languages like Python, Tcl, or Perl Excellent verbal and written communication skills Must work in person at our San Jose site and no remote work allowed Compensation and Benefits The annual base salary range for this position is To As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.