Senior Engineer II - Design

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: We are looking for a skilled and motivated Static Timing Analysis (STA) Engineer with 6 years of experience in VLSI design and timing verification. The candidate will be responsible for timing closure activities across complex SoC/IP designs and will work closely with RTL, Physical Design, DFT, and Signoff teams to ensure high-performance and power-efficient silicon implementation. Key Responsibilities: Perform block-level and full-chip Static Timing Analysis (STA) for ASIC/SoC designs. Work on timing closure during synthesis, place-and-route, and signoff stages. Develop and maintain STA constraints including SDC creation and validation. Collaborate with Physical Design and RTL teams to optimize timing, area, and power. Support ECO implementation for timing closure. Requirements/Qualifications: Bachelor’s or master’s degree in Electronics, Electrical Engineering, VLSI, or related field. 3-5 years of hands-on experience in Static Timing Analysis for ASIC/SoC designs. Strong understanding of digital design fundamentals and timing concepts. Experience with industry-standard STA tools such as PrimeTime, Tempus Good knowledge of synthesis and physical design flow. Familiarity with scripting languages such as Tcl, Perl, or Python. Strong analytical, communication, and teamwork skills. Knowledge of signal integrity and noise analysis. Travel Time: No Travel To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.