Design Verification Engineer

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. THE ROLE: The Data Accelerator (DACC) team at AMD is seeking a Silicon Design Verification Engineer who will be involved in multiple aspects of IP verification. This role is an excellent opportunity to work on next generation technologies that are part of AMD’s products powering Servers, Datacenters, Client and Embedded markets. You will join one of the fastest-growing areas of adding custom hardware offload engines to support complex operations like encryption, authentication, compression, GPU/CPU compute offloads & virtual machines live migration. This is a tremendous opportunity to get in early into the rapidly expanding domain of custom hardware accelerators. The Design Verification (DV) group within this team is responsible for developing a scalable DV flow and environment with emphasis on automation (using AI), power and performance verification (PPV) and emulation support. Our management fosters and encourages continuous technical innovation to showcase success as well as continuous career development. THE PERSON: Highly skilled in advanced ASIC Functional Verification techniques and planning. Eager to learn new designs and implementation techniques. Enjoys an environment where everyone in the team can grow and develop with a sense of global team spirit. Strong analytical thinking and problem-solving skills, excellent attention to detail. KEY RESPONSIBILITIES: Develop and maintain block level IP verification testbenches, test methodology and infrastructure Develop detailed test plans for covering new features Triage regressions, debug simulations, analyze coverage, work/resolve technical issues with design, verification and other teams to achieve verification closure Deploy industry leading verification methodologies such as UVM, formal verification etc. Take end to end ownership of key features for the projects Reproduce silicon functional bugs in simulations and/or formal verification tools Conduct and participate in code reviews PREFERRED EXPERIENCE: Hands-on hardware verification experience Proficient in Verilog, System Verilog, UVM and working in Linux and Windows environments Familiarity with the hands-on use of AI agents and skills for functional verification Excellent programming skills Familiarity with Makefiles, scripting languages like perl, python, ruby etc. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer Engineering/Electrical Engineering LOCATION : Markham, ON #LI-SL3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.