Staff Engineer Digital Design Netanya Israel

Job description

Depth knowledge of Synthesis, P&R, and STA flows Collaborate with IP & SoC project teams for IP designs Deep expertise in multi-scenario STA, timing/SDC constraint development and verification Responsible for chip timing, including Synthesis, P&R and timing regression Experience in RTL, perform simulations, linting, synthesis, logic equivalence checks, and automated test pattern generation will also be part of your responsibility A University Degree in Electrical Engineering, Microelectronics, Embedded Systems or Physics or similar technical fields. At least 4 years of experience as a VLSI Backend Engineer Hands-on experience of full RTL to GDS-II flow for complex designs Experience in scripting using TCL and Python Excellent communication skills, team player spirit Fluent English both verbally and in writing We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.