Senior Staff Engineer Design Bangalore Btp

Job description

Experienced in low-power implementation, timing analysis, constraints development, and advanced node technologies (40nm/28nm/22nm). Proficient in Shell, Perl, and TCL scripting, with a strong track record of problem-solving, cross-functional collaboration, and driving successful design closure Bachelor's or Master's degree with specialization in VLSI design Hands-on technical experience in Synthesis, Logic Equivalence Checks, Low Power Sign-off Skilled in UPF based Low Power implementations and debugging complex low-power violations Experience in constraints development, sign-off timing analysis/closure will be a plus Experience in scripting languages (shell, perl, tcl) and Make flow Understanding of 40nm/28nm/22nm technologies and associated timing closure challenges Soft Skills: Strong commitment and determination in area of expertise - Must be well organized, methodical and detail oriented Ready to accept new challenges and take necessary measures to overcome those Communicates effectively and shares information comprehensively Must be a good team player and should have desire to learn and explore We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. Our hiring decisions are based on skills and experience. Even if you don't meet every requirement, we encourage you to apply. Please let your recruiter know if you need any accommodations during the interview process. Learn more about our various contact channels and about Diversity & Inclusion at Infineon. Anand Rawal Responsible for synthesis execution, timing closure, and low-power sign-off for complex low-power SoCs targeting the IoT and MCU markets. Owned synthesis implementation and timing convergence activities at both pre-DFT and post-DFT stages for large hierarchical blocks and full-chip designs. Conducted low-power Logic Equivalence Checks (LEC) across RTL-to-Netlist (RTL2N) and Netlist-to-Netlist (N2N) stages to ensure design integrity. Led UPF-based low-power verification and sign-off across synthesis, post-layout, and final sign-off stages. Collaborated closely with architecture, RTL, and DFT teams to evaluate timing feasibility, assess performance targets, and drive design optimization. Partnered with Physical Design and STA teams to achieve post-layout timing closure and ensure successful design sign-off.