Principal Silicon Design Verification Engineer United States California Santa Clara

Job description

Functional validation of PCIe IP at Block, Cluster or Fullchip using UVM/C test bench and Verification IP (VIP) Develop Test Plan and write unit tests for functional validation Create and Manage regression suites, debug failures, and drive timely resolution Innovate to improve validation efficiency through methodologies and tools Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. Experience with protocol verification for PCIe, especially Gen6/Gen7, and related standards such as NVMe or RDMA Experience with Cluster, SoC, or Fullchip level verification Prior verification experience with PCIe, both at the Transaction and Data Link Layer Strong proficiency in Verilog, System Verilog, and UVM based testbench environment. Good understanding of computer architecture and digital design fundamentals Experience building UVM testbenches, managing regressions, meeting code coverage and functional coverage goals to succesfull tapeout.