Technical Architect

Job description

FPGA RTL Design & Validation E3.1 Candidates with 5 to 10 years’ experience is mandatory Experience in defining micro-architecture specifications for high-performance, low-power digital design blocks and subsystems. Key Responsibilities Experience in Full chip RTL integration Experience with ASIC/SoC development flow including synthesis/timing constraints development, Static Timing Analysis closure, resolving P& R congestion issues etc. Experience in RTL Synthesis Skill Requirements Scripting experience Experience integrating IP's like PCIe, DDR, Ethernet etc. Should be able to lead a team of 5 to 6 leads under whom entry level engineers will be there. Other Requirements Expected to handle minimum 2 projects simultaneously Experience in handling and interacting with clients across different Geos. Excellent communication skills are mandatory. Apply now Information at a Glance Why HCLTech? At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first. HCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June 2026 totaled $14.8 billion. Disclaimer Privacy Statement Terms of use Sitemap Raise a Grievance We use cookies on our site. Please read more about cookies policy here. Opens in a new tab. Opens in a new tab. Opens in a new tab. Opens in a new tab. Opens in a new tab. Opens in a new tab. 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