GPU Logic Design Engineer

Job description

Job Details: Job Description: The Role and Impact As a GPU Logic Design Engineer, you will play a pivotal role in developing and refining the graphics IPs that drive Intel's cutting-edge GPUs. You will be responsible for designing, coding, and simulating register transfer level (RTL) logic for critical GPU IP blocks, ensuring they meet stringent power, performance, area, and timing goals. Your contributions will directly impact the quality and functionality of Intel's GPUs, enabling unparalleled visual experiences for users worldwide. Business Group The Data Center Group (DCG) is at the heart of Intel's mission to power the future of computing. Focused on advancing data-centric solutions, DCG develops innovative hardware and software technologies that accelerate workloads for AI, cloud, and enterprise systems. Within this group, the AI SOC SCAN ATPG organization is dedicated to ensuring the delivery of high-quality, high-performance GPU designs that support Intel's leadership in graphics and visual computing. Key Responsibilities - Develop logic design and write RTL code for GPU IP blocks, focusing on graphics, compute, display, and media. - Collaborate in defining the architecture and microarchitecture features of GPU blocks. - Optimize logic designs to meet power, performance, area, and timing goals for physical implementation. - Review verification plans and drive unit-level verification to ensure correctness of design features. - Resolve RTL test failures and implement corrective measures to guarantee feature integrity. - Support SoC customers in integrating and verifying GPU blocks for high-quality SoC designs. Qualifications:Minimum Qualifications - Bachelor's degree in Electrical Engineering, Computer Engineering, or related field, with 3+ years of industry experience; OR Master's degree in the same fields, with 2+ years of industry experience; OR PhD with no industry experience. - Hands-on experience with at least one key DFT feature, such as TAP/JTAG, Scan/ATPG, or Array DFT (MBIST/PBIST). - Proficiency in using EDA tools such as ATPG tools, Mentor Tessent shell, and VCS simulation/debug tools. - Background in silicon enabling, debug, or test pattern development. Preferred Qualifications - Proficiency in programming or scripting languages for design automation. - Familiarity with structural design flows, including timing analysis, routing, placement, or clocking. - Knowledge of high-volume manufacturing requirements and test flows. - Understanding of 3D, media, and display graphics pipelines. - SoC architecture expertise. Join us to shape the future of graphics and visual computing. Bring your expertise to Intel's GPU Hardware IP team, where innovation meets impact. Job Type:Experienced Hire Shift:Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.