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Synopsys

Staff Application Engineer Mississauga, Canada Category: Engineering Posted: 09/29/2026 Job ID: 18835

Synopsys · Mississauga, Canada

Full-timeOn-sitePosted 17 October 2026
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Job description

Find Jobs For Where? Staff Application Engineer Mississauga, Ontario, Canada Apply Now Category Engineering Hire Type Employee Job ID 18835 Base Salary Range $106000-$160000 Date posted 09/29/2026 Share this job Email LinkedIn X Facebook We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the verification trenches and learned that the hardest part is not running the emulator, it is making it fit the way a customer actually works. When a testbench does not behave as expected or a model hangs three hours into a regression, you do not guess. You dig in, trace signals, check the logs, and work the problem until you understand what is actually happening. You are comfortable sitting with a customer's verification team, absorbing their constraints, their schedule pressure, their testbench quirks, and walking out with a deployment plan that actually works for them. You know the difference between a solution that looks good in a slide deck and one that survives contact with a real SoC project. Debugging across hardware models, software stacks, and verification environments does not intimidate you. It energizes you. You ask the right questions, coordinate across R&D and customer teams without losing the thread, and you do not escalate until you have exhausted what you can do yourself. At Synopsys, you will work with customers running some of the most complex verification projects in the industry, and the solutions you help implement will directly affect their ability to tape out on schedule. What You'll Be Doing Work directly with customers to deploy and optimize emulation solutions for SoC and ASIC verification projects Design emulation strategies that fit the specific architecture, testbench, and schedule constraints of each customer engagement Debug complex issues that span hardware models, software interactions, and testbench integration, working with customers and internal R&D to resolve them Build and deliver technical enablement sessions and workshops that help customers and internal teams get more out of the platform Collaborate with product engineering teams to surface customer requirements, workflow gaps, and feature requests that shape future platform releases Mentor engineers on the team, helping them build deeper technical skills in emulation methodologies and customer engagement The Impact You Will Have Shorten verification cycles for customers working on high-stakes semiconductor projects where schedule pressure is constant Increase platform adoption and effectiveness by helping customers implement workflows that actually fit their design and verification environments Influence product roadmaps by translating real customer pain points into actionable feedback for R&D teams Build long-term customer relationships grounded in technical credibility and reliable execution Raise the technical capability of the applications team by sharing what you learn and helping others work through difficult customer scenarios Strengthen Synopsys' position as the go-to provider for emulation and verification solutions in the semiconductor industry What You'll Need B.E/B.Tech in Electrical & Electronics Engineering with 7+ years in applications engineering, hardware verification, or emulation support roles, or M.S/M.Tech in Electrical & Electronics Engineering with 5+ years in similar roles Hands-on experience with emulation platforms such as Synopsys ZeBu, Mentor Veloce, or Cadence Palladium Strong working knowledge of Verilog, SystemVerilog, or VHDL and verification methodologies including UVM or OVM Demonstrated ability to debug and optimize interactions between hardware models, testbenches, and emulation infrastructure Solid understanding of SoC and ASIC architecture, including how design flows and verification environments are structured Experience with Python, Perl, or TCL for automation and workflow scripting Experience with customer-facing technical work is a strong plus Who You Are <ul style='--tw-border-spacing-x: 0; --tw-border-spacing-y: 0; --tw-translate-x: 0; --tw-translate-y: 0; --tw-rotate: 0; --tw-skew-x: 0; --tw-skew-y: 0; --tw-scale-x: 1; --tw-scale-y: 1; --tw-pan-x: ; --tw-pan-y: ; --tw-pinch-zoom: ; --tw-scroll-snap-strictness: proximity; --tw-gradient-from-position: ; --tw-gradient-via-position: ; --tw-gradient-to-position: ; --tw-ordinal: ; --tw-slashed-zero: ; --tw-numeric-figure: ; --tw-numeric-spacing: ; --tw-numeric-fraction: ; --tw-ring-inset: ; --tw-ring-offset-width: 0px; --tw-ring-offset-color: #fff; --tw-ring-color: rgb(59 130 246/0.5); --tw-ring-offset-shadow: 0 0 #0000; --tw-ring-shadow: 0 0 #0000; --tw-shadow: 0 0 #0000; --tw-shadow-colored: 0 0 #0000; --tw-blur: ; --tw-brightness: ; --tw-contrast: ; --tw-grayscale: ; --tw-hue-rotate: ; --tw-invert: ; --tw-saturate: ; --tw-sepia: ; --tw-drop-shadow: ; --tw-backdrop-blur: ; --tw-backdrop-brightness: ; --tw-backdrop-contrast: ; --tw-backdrop-grayscale: ; --tw-backdrop-hue-rotate: ; --tw-backdrop-invert: ; --tw-backdrop-opacity: ; --tw-backdrop-saturate: ; --tw-backdrop-sepia: ; --tw-contain-size: ; --tw-contain-layout: ; --tw-contain-paint: ; --tw-contain-style: ; box-sizing: border-box; border: 0px solid rgb(229, 231, 235); list-style-position: initial; list-style-image: initial; list-style-type: revert; margin: 0px; padding: 0px 0px 0px 1.5rem; color: rgb(16, 27, 35); font-family: Roboto, "Roboto Fallback"; font-size: 16px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; widows: 2; word-spacing: 0px; -webkit

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