Principal Analog Design Engineer-19318 Markham, Canada Category: Engineering Posted: 10/20/2026 Job ID: 19318

Job description

Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Job Description Date posted 10/20/2026 Category Engineering Hire Type Employee Job ID 19318 Base Salary Range $151000-$226000 Remote Eligible No Date Posted 10/20/2026 We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leadi ng silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years designing circuits that operate at the edge of what physics allows, and you know that the difference between a PHY that meets spec and one that ships is usually traced back to a layout decision, a bias choice, or a parasitic you anticipated six months earlier. You are the kind of engineer who reads JEDEC standards not to check a box but to find the constraints that matter, then architects around them. You are comfortable moving between SPICE simulations, layout reviews, and whiteboard sessions with digital designers without losing sight of what you are building. When someone says "we need better power efficiency," you do not nod and move on. You ask which corner, which mode, and what we are willing to trade. You have designed enough VCOs, PLLs, samplers, or drivers to know what breaks under process variation, and you catch it before tape-out. **Other locations can be considered for this opportunity but must reside in Canada. What You'll Be Doing * Review JEDEC standards to define analog and mixed-signal sub-block specs for DDR/LPDDR, HBM, UCIe, and mobile storage PHY IP * Design transistor-lev el circuits including equalizers, samplers, drivers, serializers, VCOs, PLLs, DLLs, bandgap references, ADCs, and DACs * Develop verification strategies using SPICE simulators and Verilog-A models to ensure coverage across PVT corners * Collaborate with layout engineers to minimize parasitics, manage device stress, and implement ESD protection * Present simulation data and design tradeoffs to internal teams and customers * Document circuit designs, test plans, and reliability considerations for tape out * Consult on electrical characterizati on and silicon bring-up to validate your circuits in the final product The Impact You Will Have * Enable next-generatio n memory and interconnect solutions that define performance benchmarks for DDR, LPDDR, and HBM standards * Deliver power-efficien t, high-speed analog circuits in advanced FinFET nodes * Reduce tape out risk through rigorous simulation and early identification of layout issues * Influence circuit architecture decisions that shape Synopsys Solution IP product roadmaps * Contribute to IP products that accelerate customer time to market for AI, mobile, automotive, and data center applications What You'll Need * PhD with 6+ years or Master's with 8+ years of analog and mixed-signal IC design experience * Deep expertise in transistor-lev el CMOS design with strong fundamentals in device physics and matching * Proven experience designing circuits in FinFET process technologies * Detailed design experience with high-speed sub-circuits: equalizers, samplers, drivers, serializers, VCOs, PLLs, DLLs, bandgaps, ADCs, or DACs * Working knowledge of ESD protection techniques and layout strategies * Proficiency with schematic entry, SPICE simulation (Spectre, HSPICE), and design verification tools * Strong understanding of design-for-rel iability including electromigrati on, IR drop, aging, and layout-depende nt effects Who You Are * You can look at a circuit topology and immediately identify the second-order effects that will matter at corner cases * You communicate tradeoffs clearly, whether explaining a bias decision to a layout engineer or presenting jitter analysis to customers * You push back when a specification does not make physical sense, and you do it in a way that moves the team forward * You are comfortable scripting in Python, Perl, TCL, MATLAB, or C to automate simulation flows and build custom analysis tools * You document your work clearly enough that someone else can pick up your design six months later and understand why you made each decision The Team You'll Be Part Of <br style='outline: 0px; margin: 0px; color: rgb(0, 28, 67); font-family: "IBM Plex Sans"; font-size: 12px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; white-space: normal; text-decoration-thickness: initial;