Senior Solution Architect

Job description

Lead and own SoC RTL integration for complex chips, ensuring seamless assembly of multiple IPs/subsystems into a functionally correct, synthesis-ready top-level design. This role is central to aligning architecture, design, verification, and physical teams for successful tape out. 🎯 Key Responsibilities 🔹 RTL Integration Ownership Own top-level RTL integration of SoC: Integrate multiple IPs, subsystems, and third-party blocks Ensure clean connectivity, hierarchy, and modular structure Deliver synthesis-ready, lint-clean, and CDC-clean RTL 🔹 Architecture Alignment Work closely with architecture teams to: Translate SoC architecture into RTL structure Ensure correct implementation of: Interconnects (NoC / bus-based) Address maps Reset and clock architecture 🔹 Interface & Connectivity Management Define and validate: IP interfaces and protocols (AXI, AHB, APB, etc.) Address decoding and interconnect connectivity Resolve: Interface mismatches Integration conflicts across teams 🔹 Clock, Reset & Power Integration Key Responsibilities Define and integrate: Clocking architecture (multiple clock domains) Reset strategies (global/local resets) Power domains (UPF/CPF alignment) Ensure: Clean CDC/RDC implementation Proper low-power intent integration 🔹 Quality & Signoff Readiness Drive RTL quality checks: Lint (SpyGlass, Lint tools) CDC/RDC analysis Basic synthesis checks Ensure RTL is: DV-ready DFT-ready PD-friendly 🔹 Collaboration Across Teams Interface with: IP/RTL design teams DV teams (for testbench integration support) DFT teams (for scan/test readiness) PD/STA teams (for implementation alignment) Act as central integration point across all domains 🔹 Debug & Issue Resolution Lead debug of: Integration bugs Boot-up and reset sequence issues Connectivity and functional mismatches Support system-level bring-up in simulation/emulation 🔹 Automation & Flow Development Develop scripts/tools for: RTL stitching Connectivity checks Build and regression flows Improve integration efficiency and repeatability Skill Requirements 🔹 Leadership Lead and mentor RTL integration engineers Drive integration schedules, milestones, and reviews Act as owner of top-level RTL quality and readiness 🧰 Required Skills & Expertise 🔸 Technical Strong expertise in: Verilog/SystemVerilog RTL design SoC integration and architecture Deep understanding of: Bus protocols (AXI/AHB/APB) Clock/reset domain design Low-power design (UPF/CPF basics) Experience with: Lint, CDC/RDC tools Synthesis awareness 🔸 Experience 15–18+ years in RTL design/integration Proven experience in: Chip-level RTL integration ownership Multiple SoC tapeouts Other Requirements 🔸 Tools Lint: SpyGlass / Questa Lint CDC: SpyGlass CDC / Questa CDC Synthesis: Design Compiler / Genus (basic awareness) Version control: Git/Perforce 🔸 Soft Skills Strong system-level thinking Excellent coordination across large teams Problem-solving and debugging mindset 🏆 Good to Have Experience in: NoC-based SoC architectures Emulation/FPGA bring-up Firmware/boot flow understanding Scripting: Python / TCL / Perl 📊 Success Metrics Clean, integration-ready RTL (lint/CDC clean) Smooth handoff to DV, DFT, and PD teams Minimal integration bugs at system level Predictable integration schedules First-pass success in SoC bring-up Apply now Information at a Glance Why HCLTech? At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first. HCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June 2026 totaled $14.8 billion. Disclaimer Privacy Statement Terms of use Sitemap Raise a Grievance We use cookies on our site. Please read more about cookies policy here. Opens in a new tab. Opens in a new tab. Opens in a new tab. Opens in a new tab. Opens in a new tab. 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