Senior Technical Lead

Job description

Candidates with more than 8 years’ experience is mandatory. Own the firmware and embedded software that makes high-speed interfaces train, stay up, and present a usable device or root-complex to the rest of the system. The primary interface family is PCI Express. It also covers related stacks such as CXL, USB4 / USB SuperSpeed, Ethernet MAC/PCS software where the work is link bring-up rather than a full networking product, and similar controller-plus-PHY designs. Key Responsibilities Lead firmware and embedded software for PCIe and similar interfaces from architecture through first successful link-up on silicon or a representative FPGA / emulation platform. Own controller firmware and link bring-up: LTSSM (or equivalent state machine), speed negotiation, equalization, lane configuration, reset and recovery, error logging, and power states that the interface actually implements. Own the embedded software that sits above that firmware: Linux or RTOS driver, endpoint or root-complex HAL, configuration space / BAR bring-up, basic DMA path, and a golden traffic test the lab can run. Work the boundary with hardware and validation: when a link will not train, decide whether the next action is PHY, controller firmware, host software, board, or the other end of the cable. Define registers, firmware interfaces, and logs so validation and SoC firmware can debug without you in every meeting. Interfaces in scope Core: PCI Express (device, root complex, or switch port software — whichever the program needs). Adjacent, same skill: CXL, USB4 / USB SuperSpeed, SATA / SAS controller software, Ethernet MAC/PCS bring-up, die-to-die controller software where the job is link state and driver enablement. Skill Requirements Experience in firmware and/or embedded software on high-speed interfaces, with PCIe or similar high speed interface. At least one program owned and technically executed end-to-end: accountable for the interface firmware and software that took a controller from reset to a trained link and a usable software path (enumeration, a BAR or equivalent, and traffic — not only “LTSSM reached L0 in a log”). Working depth in PCIe link bring-up (LTSSM, speeds, equalization concepts, AER / error handling, config space) and in writing the driver or firmware that operates the controller. Able to read a controller programming guide and a PHY datapack and produce working bring-up code, not only a design presentation. Experience with lab tools used on these links (protocol analyzer, BERT where relevant, vendor PHY utilities) enough to partner with validation. Other Requirements Must have skills - Firmware and/or platform software Good to have skills PCIe Gen5 or Gen6, or CXL 1.1 / 2.0 / 3.x software bring-up on real silicon. Both endpoint and root-complex software experience. Controller firmware running on an embedded core inside the interface block, not only a Linux host driver. SR-IOV, IOMMU / SMMU programming for the interface, or tight coupling with a custom DMA engine. Multi-die or chiplet link software (UCIe or vendor equivalent) as firmware/driver work. Led a distributed team across a customer lab and an offshore design center Apply now Information at a Glance Why HCLTech? At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first. HCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. 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