Senior Design Lead

Job description

Job Summary We are seeking a Senior SoC Design Engineer with 7 -10 years of experience in ASIC/SoC design and deep expertise in one or more next-generation compute, memory, interconnect, or coherency technologies. The candidate will be responsible for micro-architecture, RTL design, IP/subsystem development, and SoC integration for complex SoCs used in AI/ML, Datacenter, HPC, Networking, and Server platforms. Key Responsibilities Key Responsibilities Design and develop RTL for complex ASIC/SoC subsystems using Verilog/SystemVerilog. Own micro-architecture definition, RTL implementation, and design reviews. Develop and integrate high-performance IPs, interconnects, memory subsystems, and coherency fabrics. Collaborate with Architecture, Verification, Physical Design, DFT, Firmware, and Validation teams. Drive design quality through lint, CDC/RDC, synthesis, and timing closure support. Support SoC integration, bring-up, and silicon debug activities. Participate in performance, power, and area optimization initiatives. Required Skills Strong hands-on experience in RTL Design using Verilog/SystemVerilog . Good understanding of ASIC/SoC design lifecycle and multiple tape-outs. Experience in micro-architecture development and RTL implementation. Knowledge of synthesis, LEC, CDC/RDC, STA, and low-power design concepts. Strong debugging and problem-solving skills. Exposure to scripting using Python, Perl, TCL, or Shell. Skill Requirements null Other Requirements Niche Skill Requirements (One or More Preferred) High-Speed Interfaces & Memory Subsystems PCIe Gen5/Gen6 CXL (Compute Express Link) UCIe LPDDR5/LPDDR6 HBM3/HBM4 DDR5 Memory Controllers Ethernet (100G/400G/800G) High-Speed SerDes Design USB4 / Thunderbolt ARM & Coherency Architectures ARM Neoverse Compute Platforms AMBA AXI/AHB/APB ARM CHI / CHI-E ACE / ACE-Lite Coherent Mesh Networks (CMN) Cache Coherency Fabric Design Multi-Core CPU Subsystem Integration Advanced Compute & Datacenter SoCs AI/ML Accelerator Architecture NPU/GPU Subsystems Network-on-Chip (NoC) Datacenter and Server SoCs HPC Processor Subsystems Virtualization Support RAS (Reliability, Availability, Serviceability) Security and TrustZone Architecture Functional Safety Architectures Preferred Skills Low-Power Design (UPF/CPF). Experience with ARM-based SoC implementations. Knowledge of performance modeling and architecture trade-off analysis. Experience in AI Accelerator, Networking, Datacenter, or Automotive SoCs. Exposure to FPGA prototyping and post-silicon debugging. Apply now Information at a Glance Why HCLTech? At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first. HCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June 2026 totaled $14.8 billion. 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