Technical Architect

Job description

We are seeking a senior Full-Chip Low Power Verification / VCLP Engineer to lead the architectural integration and static low-power sign-off for massive, complex multi-core SoCs. In this role, you will be responsible for defining the hierarchical Unified Power Format ( UPF ) strategy and executing Synopsys VC LP at the full-chip level. You will validate the interaction between sub-chip macros, top-level routing, analog/IP interfaces, power-management units (PMU), and Always-On (AON) domains, ensuring 100% silicon safety against power-state architectural bugs before tape-out. Key Responsibilities UPF Strategy & Writing: Develop, refine, and maintain Unified Power Format ( UPF 1.0, 2.0, or 3.0 ) specifications across various hierarchy levels (Block, Subsystem, and SoC). Static Low Power Verification: Execute block-level and full-chip low-power static checks using Synopsys VC LP at multiple stages (RTL, pre-layout netlist, and post-route gates). Error Debugging & Resolution: Troubleshoot and root-cause complex VC LP structural errors and warnings, including missing isolation cells, incorrect level shifter ranges, mismatched power domains, and floating signals. Cross-Functional Sync: Collaborate closely with RTL Front-End Architects, Power Management teams, Place & Route (PnR) Implementation Engineers, and Formal Verification (LEC) teams to resolve low-power implementation discrepancies. Flow Automation & Scripting: Enhance, maintain, and scale static low-power verification regressions by building custom automation scripts using TCL and Python . Methodology Definition: Create comprehensive low-power waiver policies, review waivers periodically, and establish best-practice guidelines for low-power design constraints. Skill Requirements 1.Low power design Techniques Multi – VDD Power gating – PSO Dynamic Voltage and Frequency Scaling (DVFS) Retention registers Isolation cells (ISO) Level Shifters (LS). 2. Synopsys VC LP (or equivalent static low-power checkers) or Cadence Conformal LP or Siemens Questa LP. 3. scripting: TCL/perl/Python Other Requirements Apply now Information at a Glance Why HCLTech? At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first. HCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June 2026 totaled $14.8 billion. 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