Senior Technical Architect

Job description

Senior Signal and Power Integrity Engineer Microsoft's mission is to empower every person and every organization on the planet to achieve more. At Microsoft Quantum, we aim to empower science and scientists to solve the world's biggest problems by realizing advanced computing platforms at the intersection of high-performance computing, artificial intelligence (AI), and quantum information technology. For more information about our team, visit https://www.microsoft.com/en-us/quantum We are seeking a Senior Signal and Power Integrity Engineer to work in dynamic cross-functional role to optimize ASIC, package, PCB for mixed signal circuits. The candidate will have SI and PI ownership throughout the entire life-cycle of hardware that sits at the intersection of electrical, mechanical, thermal analysis, and RF engineering. Working within the cryogenic complementary metal‑oxide semiconductor (cryo‑CMOS) team, you will have the opportunity to make a significant impact on a revolutionary technology. We are looking for an SI engineer responsible for signal integrity and power integrity designs for ICs and packages (substrates, interposers, redistribution layers, etc.). The work will include everything from IP evaluation in the silicon architecture stage, package performance evaluation, interconnect layer stackup selection and characterization, channel and PDN architecture, and PCB layout oversight. Key Responsibilities Responsibilities Responsible for signal and power integrity portion of cryogenic ASICs, package, PCB, connector and cables. Model and simulate end-to-end high-speed channels including transceivers, IC package, PCB and cross-boards connectors/cables Utilize industry-standard tools and methodologies to perform a variety of time/frequency domain signal integrity analysis (SPICE, full-wave EM analysis, etc) Identify the link quality such as loss, reflection and crosstalk, and resolve the issues across transition structures for the entire channel i.e. die bump, package BGA, PCB, connector and cables. Interpret the simulation results to provide the design guidelines on board materials, stack-up, transmission line routings, component placement and layout optimization Define best practices, simulation workflows, test methodologies, signoff criteria, and lab equipment needs for all SI/PI requirements Collaborate closely with multidisciplinary partners—including ASIC designers, electrical engineers, and qubit measurement engineers—to inform and optimize system design. Embody our Culture and Values Skill Requirements Qualifications Required/Minimum Qualifications Master's Degree in Electrical Engineering, or related field. OR Bachelor's Degree in Electrical Engineering, or related field AND 2+ years experience in industry or in a research and development environment OR equivalent experience. 4+ years of experience in technical organizations in IC design and packaging environments. Deep knowledge and experience applying EE fundamentals, EM theory, and coupling mechanisms in circuit or system design, analysis, or troubleshooting. Hands-on experience with simulation and analysis of transmission lines, channel modeling, and signal/power integrity Expertise with EDA tools (e.g., Ansys HFSS, Q3D, SiWave, Cadence PowerSI, Clarity, PowerDC, Allegro, APD, Spectre, Keysight ADS, Synopsys Hspice). Experience in SI analysis of interposers and/or advanced packages (e.g., FCBGA, chiplet-based, CoWoS, 2.5D, 3D architectures). Practical experience in interpreting measurements from VNA and oscilloscopes Other Requirements Other requirements Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Ability to work in an “AI-first” environment using modern AI tools to accelerate discovery through both hardware and software development. Ability to design and build AI agents/copilots that assist with experiment setup, log triage, measurement report generation, protocol templating, and knowledge retrieval (e.g. instrument manuals, design docs). Additional/Preferred Qualifications The ideal candidate will also have: Doctorate in Electrical Engineering, or related field 6+ years experience in power integrity and signal integrity field designing, implementing, and debugging power delivery networks for large processors, FPGAs, SoC, or ASICs with complex power requirements Experience with analog electronic circuit design. Knowledge of on-chip power analysis flow (e.g., PTPX, Redhawk, Voltus), SoC physical design (e.g. floor plan). Experience with scripting for data collection and analysis (e.g., Python, bash). Experience debugging and resolving EMI/EMC de-sense problems Experience with IC packaging in extreme environments and/or cryogenic temperatures. Strong teamwork and communication skills. Ability to adapt and operate effectively in a rapidly changing research environment. Demonstrated experience with technical report writing and documentation. Experience with cross‑team collaboration and/or mentoring. #Quantum #QuantumCareers #MDQCareers Additional Information Location: Redmond, Washington, USA Travel: 0–25% MICROSOFT BACKGROUND CHECK: Ability to meet Microsoft, customer, and/or government security screening requirements is required for this role. This position will require passing the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations, and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. Maximum Salary (US): 192000 Minimum Salary (US): 95000 Apply now Information at a Glance Why HCLTech? At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first. HCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June