Verification Design Engineer Boxborough, Massachusetts Category: Engineering Posted: 10/25/2026 Job ID: 19066

Job description

Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Job Description Date posted 10/25/2026 Category Engineering Hire Type Employee Job ID 19066 Base Salary Range $138000-$208000 Remote Eligible No Date Posted 10/25/2026 We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, enabling everything from self-driving cars to AI-powered systems. We lead in chip design, verification, and IP integration, empowering innovators to create high-performance silicon and software solutions. Join us and help shape the future of technology. You Are A highly experienced design verification engineer with deep expertise in verifying complex digital IP and high-speed interfaces. You bring strong experience in SystemVerilog, UVM, coverage-driven verification, and debug , along with knowledge of technologies such as DDR, UCIe, PHY, or SERDES . You thrive on solving complex verification challenges and driving high-quality IP from initial architecture through verification closure. What You’ll Be Doing Develop and execute verification strategies for PHY, DDRIO, UCIe, and other high-speed interface IP . Architect and develop SystemVerilog/UVM testbenches , verification environments, test plans, and reusable verification components. Create directed and constrained-random tests, assertions, functional coverage, and coverage models. Drive functional and code coverage closure , regression analysis, and verification signoff. Debug complex RTL, protocol, testbench, and system-level issues in partnership with design engineers. Verify block- and subsystem-level functionality, including interfaces, resets, clocking, low-power behavior, and error scenarios. Collaborate closely with RTL design, architecture, firmware, modeling, and implementation teams. Mentor engineers and help drive verification methodology and best practices. The Impact You Will Have Ensure the quality and robustness of next-generation high-speed connectivity IP. Identify complex functional and protocol issues early in the development cycle. Improve verification efficiency, coverage, reuse, and overall product quality. Contribute to industry-leading PHY and interface IP used in advanced semiconductor products. Strengthen verification methodologies and technical expertise across the engineering organization. What You’ll Need Required Qualifications BS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant experience , or MS with 10+ years of experience . Strong experience in ASIC/IP design verification . Advanced proficiency with SystemVerilog and UVM . Experience developing verification environments, test plans, assertions, functional coverage, and constrained-random tests. Strong RTL and waveform debugging skills. Experience with PHY, DDR/DDRIO, UCIe, SERDES, PCIe, CXL, or similar high-speed interface technologies . Understanding of the complete ASIC/IP development and verification lifecycle. Strong analytical, problem-solving, and communication skills. Preferred Qualifications Experience verifying complex IP at the block and subsystem level . Experience with coverage-driven verification and verification closure. Familiarity with low-power verification, clock/reset verification, and protocol checking . Experience with industry-standard simulation, debug, coverage, and verification tools. Experience mentoring engineers or providing technical verification leadership. Who You Are A verification engineer who enjoys finding difficult corner cases before they become silicon issues. A strong debugger who can work across RTL, testbench, protocol, and system boundaries. A collaborative technical partner to design and architecture teams. A self-starter who can independently drive verification from planning through closure. A mentor who raises the technical capability of the broader team. The Team You’ll Be A Part Of You will join a team developing next-generation PHY and high-speed interface IP . Working closely with architecture, RTL design, verification, and implementation teams, you will help ensure complex IP meets demanding functional, performance, and quality requirements. Rewards and Benefits Synopsys offers a comprehensive and competitive benefits package designed to support your health, wellbeing, and financial future. Your recruiter can provide additional details regarding compensation, benefits, and total rewards during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S. Apply Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Boxborough View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You’ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you’re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys! BROWSE JOBS Find the open role that’s right for you Hardware Security Analyst - Semiconductor IP Bengaluru, India Verification Design Engineer Boxborough, Massachusetts Senior Technical Product Engineer - Implementation Sunnyvale, California Hardware Engineer