Applications Engineering, Sr Staff Engineer_PERC Hsinchu, Taiwan Category: Engineering Posted: 11/10/2026 Job ID: 18945

Job description

Applications Engineering, Sr Staff Engineer_PERC Hsinchu, Taiwan Apply Now Category Engineering Hire Type Employee Job ID 18945 Date posted 11/10/2026 Share this job • Email • LinkedIn • X • Facebook We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent over a decade deep in the physics and practicalities of what makes chips fail, and you know that reliability verification is where theory meets the real world of manufacturing constraints, ESD events, and voltage domains that do not play nicely together. The difference between a chip that ships and one that does not often comes down to a latch-up path someone missed or an ESD structure that looked fine in simulation but failed in silicon, and you are the kind of engineer who catches those before tape-out. You do not just run checks, you build the rule decks that define them. You have worked with foundry DRMs that read like legal documents, translated reliability specs into verification flows, and debugged why a perfectly valid design triggered a false positive at 3nm. You speak the language of process engineers and design teams equally well, and you know how to turn a foundry's reliability requirements into something a customer can actually use. Working with foundries energizes you. You thrive in the technical back-and-forth of defining what needs to be checked, why it matters, and how to make it scalable. At Synopsys, you will shape the reliability verification methodologies that enable the most advanced semiconductor technologies in production today. What You'll Be Doing • Develop, maintain, and optimize PERC rule decks for advanced process nodes, translating foundry reliability specifications into scalable verification flows • Collaborate directly with foundries to understand process technologies, reliability constraints, and design rule methodologies that define signoff requirements • Partner with Synopsys R&D and Product Management teams to define product capabilities, influence roadmap priorities, and close gaps between customer needs and tool functionality • Build and deploy reliability verification flows covering ESD, latch-up, voltage-aware checks, EOS, and emerging reliability requirements for sub-5nm technologies • Support Application Engineering and customers in deploying PERC solutions, troubleshooting complex verification issues, and optimizing runtime and accuracy • Drive technical discussions with leading semiconductor companies on reliability signoff methodologies, representing Synopsys as the subject matter expert • Analyze customer requirements and translate them into verification methodologies that work across diverse design styles, IP blocks, and manufacturing processes The Impact You Will Have • Enable first-pass silicon success for customers designing at the most advanced process nodes by delivering reliable, accurate verification solutions • Strengthen Synopsys' position as the industry standard for reliability signoff and physical verification across foundries and fabless companies • Accelerate customer adoption of PERC across 3nm, 2nm, and future nodes by building rule decks that are both comprehensive and practical to deploy • Define next-generation reliability methodologies required for increasingly complex multi-die systems, advanced packaging, and heterogeneous integration • Build strategic technical relationships with foundries and ecosystem partners that shape how the industry approaches reliability verification • Influence Synopsys product roadmaps through direct engagement with customers, foundries, and internal teams, ensuring tools evolve to meet real-world needs • Reduce time-to-market for customers by delivering verification flows that catch reliability issues early, before they become silicon respins What You'll Need • 15+ years of hands-on experience in semiconductor design, EDA, physical verification, or reliability verification roles • BS or MS in Electrical Engineering, Computer Engineering, Physics, or a related technical discipline • Deep expertise in reliability verification methodologies including ESD verification, latch-up analysis, electrical rule checking, voltage-aware verification, and EOS reliability checks • Extensive experience developing PERC, DRC, LVS, or reliability verification rule decks for advanced process nodes • Strong understanding of advanced-node semiconductor manufacturing technologies, including FinFET, GAA, and emerging device architectures • Experience working with foundry PDKs, design rule manuals, and translating reliability specifications into executable verification rules • Proficiency in scripting and coding for verification rule development, using languages such as Python, Tcl, or SVRF/PVS/Calibre rule syntax Who You Are <ul style='--tw-border-spacing-x: 0; --tw-border-spacing-y: 0; --tw-translate-x: 0; --tw-translate-y: 0; --tw-rotate: 0; --tw-skew-x: 0; --tw-skew-y: 0; --tw-scale-x: 1; --tw-scale-y: 1; --tw-pan-x: ; --tw-pan-y: ; --tw-pinch-zoom: ; --tw-scroll-snap-strictness: proximity; --tw-gradient-from-position: ; --tw-gradient-via-position: ; --tw-gradient-to-position: ; --tw-ordinal: ; --tw-slashed-zero: ; --tw-numeric-figure: ; --tw-numeric-spacing: ; --tw-numeric-fraction: ; --tw-ring-inset: ; --tw-ring-offset-width: 0px; --tw-ring-offset-color: #fff; --tw-ring-color: rgb(59 130 246/0.5); --tw-ring-offset-shadow: 0 0 #0000; --tw-ring-shadow: 0 0 #0000; --tw-shadow: 0 0 #0000; --tw-shadow-colored: 0 0 #0000; --tw-blur: ; --tw-brightness: ; --tw-contrast: ; --tw-grayscale: ; --tw-hue-rotate: ; --tw-invert: ; --tw-saturate: ; --tw-sepia: ; --tw-drop-shadow: ; --tw-backdrop-blur: ; --tw-backdrop-brightness: ; --tw-backdrop-contrast: ; --tw-backdrop-grayscale: ; --tw-backdrop-hue-rotate: ; --tw-backdrop-invert: ; --tw-backdrop-opacity: ; --tw-backdrop-saturate: ; --tw-backdrop-sepia: ; --tw-contain-size: ; --tw-contain-layout: ; --tw-contain-paint: ; --tw-contain-style: ; box-sizing: border-box; border: 0px solid rgb(229, 231, 235); list-style-position: initial; list-style-image: initial; list-style-type: revert; margin: 0px; padding: 0px 0px 0px 1.5rem; color: rgb(16, 27, 35); font-family: Roboto, "Roboto Fallback"; font-size: 16px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; widows: 2; word-sp