ThessalonikiSteliou Kazantzid RF Analog Layout Engineer FinFET Technology

Job description

Job Description We are looking for an RF-focused Analog Layout Engineer with expertise in FinFET nodes. The candidate will design layouts for high-frequency analog/RF blocks, ensuring optimal performance under stringent parasitic and matching constraints. Key Responsibilities Layout design for RF circuits such as LNAs, mixers, VCOs, and PLL sub-blocks in FinFET technology. Optimize routing for high-frequency signals, minimizing parasitic capacitance and inductance. Implement shielding strategies (coaxial, differential, ground shields) to reduce coupling and crosstalk. Address EM/IR reliability for high-current RF paths and ensure compliance with advanced DRC/LVS rules. Apply matching techniques for RF differential pairs and passive components (inductors, capacitors). Collaborate with RF designers to meet performance targets for gain, noise figure, and phase noise. Ensure compliance with color-aware routing and multi-patterning constraints for RF metal layers. Job Requirements Hands-on experience in RF layout design at FinFET nodes. Deep understanding of parasitic control for high-frequency circuits. Familiarity with EM modeling, substrate coupling, and isolation techniques. Proficiency in RF-aware EDA tools and post-layout simulation flows. Knowledge of reliability and aging effects in RF devices and mitigation strategies. Preferred Skills Experience with RF sign-off flows and EM extraction tools. Ability to optimize layout for low phase noise and high linearity. Scripting skills for RF layout automation and verification.