Senior Designer

Job description

Experience: 5+ years Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.) Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV Analyze and resolve timing violations across hierarchical boundaries 🔹 Constraint Management Define and validate SDC constraints for chip-level integration Ensure proper timing budgeting and partitioning across blocks Review and align block-level constraints with chip-level requirements 🔹 Signoff & Methodology Lead signoff STA using tools like: Synopsys PrimeTime Cadence Tempus Implement and improve: MCMM (Multi-Corner Multi-Mode) flows SI-aware analysis (crosstalk, noise) ECO strategies for timing closure Ensure timing correlation between block and top level 🔹 Debug & Optimization Perform deep analysis on: Critical paths False/multicycle paths Clock domain crossings (CDC timing perspective) Drive timing ECOs with minimal impact on power/area 🔸Strong expertise in: STA fundamentals (setup/hold, skew, jitter, latency) OCV/AOCV/POCV concepts SI effects and derates Hands-on experience with: Synopsys PrimeTime / Cadence Tempus Deep understanding of: Clock tree design and analysis Low power (UPF/CPF) impact on timing Advanced nodes (7nm, 5nm preferred) Experience in hierarchical STA flows Exposure to automation (TCL/Python scripting) Knowledge of EM/IR and physical effects on timing Experience working with global teams / customers Zero/near-zero timing violations at tapeout Clean signoff across all modes/corners Predictable timing closure cycles Strong correlation between block and top-level timing Key Responsibilities JD for STA: Experience: 5+ years Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.) Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV Analyze and resolve timing violations across hierarchical boundaries 🔹 Constraint Management Define and validate SDC constraints for chip-level integration Ensure proper timing budgeting and partitioning across blocks Review and align block-level constraints with chip-level requirements 🔹 Signoff & Methodology Lead signoff STA using tools like: Synopsys PrimeTime Cadence Tempus Implement and improve: MCMM (Multi-Corner Multi-Mode) flows SI-aware analysis (crosstalk, noise) ECO strategies for timing closure Ensure timing correlation between block and top level 🔹 Debug & Optimization Perform deep analysis on: Critical paths False/multicycle paths Clock domain crossings (CDC timing perspective) Drive timing ECOs with minimal impact on power/area 🔸Strong expertise in: STA fundamentals (setup/hold, skew, jitter, latency) OCV/AOCV/POCV concepts SI effects and derates Hands-on experience with: Synopsys PrimeTime / Cadence Tempus Deep understanding of: Clock tree design and analysis Low power (UPF/CPF) impact on timing Advanced nodes (7nm, 5nm preferred) Experience in hierarchical STA flows Exposure to automation (TCL/Python scripting) Knowledge of EM/IR and physical effects on timing Experience working with global teams / customers Zero/near-zero timing violations at tapeout Clean signoff across all modes/corners Predictable timing closure cycles Strong correlation between block and top-level timing Skill Requirements JD for STA: Experience: 5+ years Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.) Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV Analyze and resolve timing violations across hierarchical boundaries 🔹 Constraint Management Define and validate SDC constraints for chip-level integration Ensure proper timing budgeting and partitioning across blocks Review and align block-level constraints with chip-level requirements 🔹 Signoff & Methodology Lead signoff STA using tools like: Synopsys PrimeTime Cadence Tempus Implement and improve: MCMM (Multi-Corner Multi-Mode) flows SI-aware analysis (crosstalk, noise) ECO strategies for timing closure Ensure timing correlation between block and top level 🔹 Debug & Optimization Perform deep analysis on: Critical paths False/multicycle paths Clock domain crossings (CDC timing perspective) Drive timing ECOs with minimal impact on power/area 🔸Strong expertise in: STA fundamentals (setup/hold, skew, jitter, latency) OCV/AOCV/POCV concepts SI effects and derates Hands-on experience with: Synopsys PrimeTime / Cadence Tempus Deep understanding of: Clock tree design and analysis Low power (UPF/CPF) impact on timing Advanced nodes (7nm, 5nm preferred) Experience in hierarchical STA flows Exposure to automation (TCL/Python scripting) Knowledge of EM/IR and physical effects on timing Experience working with global teams / customers Zero/near-zero timing violations at tapeout Clean signoff across all modes/corners Predictable timing closure cycles Strong correlation between block and top-level timing Other Requirements JD for STA: Experience: 5+ years Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.) Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV Analyze and resolve timing violations across hierarchical boundaries 🔹 Constraint Management Define and validate SDC constraints for chip-level integration Ensure proper timing budgeting and partitioning across blocks Review and align block-level constraints with chip-level requirements 🔹 Signoff & Methodology Lead signoff STA using tools like: Synopsys PrimeTime Cadence Tempus Implement and improve: MCMM (Multi-Corner Multi-Mode) flows SI-aware analysis (crosstalk, noise) ECO strategies for timing closure Ensure timing correlation between block and top level 🔹 Debug & Optimization Perform deep analysis on: Critical paths False/multicycle paths Clock domain crossings (CDC timing perspective) Drive timing ECOs with minimal impact on power/area 🔸Strong expertise in: STA fundamentals (setup/hold, skew, jitter, latency) OCV/AOCV/POCV concepts SI effects and derates Hands-on experience with: Synopsys PrimeTime / Cadence Tempus Deep understanding of: Clock tree design and analysis Low power (UPF/CPF) impact on timing Advanced nodes (7nm, 5nm preferred) Experience in hierarchical STA flows Exposure to automation (TCL/Python scripting) Knowledge of EM/IR and physical effects on timing Experience working with global teams / customers Zero/near-zero timing violations at tapeout Clean signoff across all modes/corners Predictable timing closure cycles Strong correlation between block and top-level timing Apply now Information at a Glance Why HCLTech? At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first. HCLTech is a global technology company, home to more than 230,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending September 2026 totaled $14.8 billion. Disclaimer Privacy Statement Terms of use Sitemap Raise a Grievance We use cookies on our site. Please read more about cookies policy here. Opens in a new tab. Opens in a new tab. Opens in a new tab. Opens in a new tab. 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